The invention relates to a monolithically integratable transmission system for binary information comprising at least one address source that is connected via an address bus to at least one address sink. At least one register means for write-in and read-out of binary coded data respectively allocated to an address sink is activatable via a respective selection line and is connected to a data bus. A clock generator for generating two phase-shifted, non-overlapping clock signals is provided. A first precharging unit for precharging the data bus is driven in accordance with a first clock signal and a register means for write-in and read-out of binary coded data is addressed in accordance with a second clock signal.
It is known in the construction of data processing systems to provide bus-oriented transmission systems which comprise an address bus and a data bus. A first bus structure may be characterized by a central address bus which is connected to a plurality of decentralized decoders for the selection of a register means. Another typical system structure comprises a central address decoder from which control lines lead in star-like fashion to a plurality of register units.
Dependent on their length, all signal lines of the transmission system are affected by an undesired transient response behavior given application of signals. In order to guarantee that all transients have ended given application of address and data signals, the output and reception of signals requires a strictly synchronous clocking.
A stable signal level can be achieved in a short time since the corresponding signal line is precharged with a high level that can be discharged in a short time under given conditions in accordance with the signal pattern. In a two-clock system, the data bus is precharged in a first clock phase while the address is connected to the address bus. The control signals decoded therefrom must be stable before the end of the first phase. In the second phase, the data pattern is connected to the precharged data bus, whereas the address bus remains stable.
As short as possible a discharging or charging time of the address bus is desired in order to increase the switching speed. The time available for this purpose, given an address change, is identical for both operations, so that a charging operation in NMOS technology requires a longer time than a discharging operation for physical reasons. A charging transistor must be dimensioned relatively large in order to equalize the time difference. This results in a correspondingly larger surface requirement and power consumption, this being particularly felt given a system structure having a plurality of address sources. There is also the danger that signals from a plurality of signal sources will overlap and that high current spikes thus arise.